Kepler Computing, a San Jose startup that has operated in stealth for approximately eight years, announced Tuesday it has raised $468 million to manufacture AI memory chips using a composite ferroelectric material that sidesteps the most advanced—and scarce—semiconductor manufacturing equipment. The company's backers include GlobalFoundries, Intel Capital, AMD Ventures, Baillie Gifford, and Gates Frontier, according to Wired, which first reported the news. In July, Kepler also secured a letter of intent from the National Institute of Standards and Technology that may provide up to $245 million in federal CHIPS Act research funding, though final award amounts may differ after due diligence.
The pitch is straightforward, if audacious: Kepler believes it can build high-performance memory for artificial intelligence using mature 28-nanometer manufacturing processes at GlobalFoundries facilities in Singapore and Burlington, Vermont. That approach, the company says, would bypass the capacity constraints that have turned high-bandwidth memory into the primary chokepoint for AI hardware expansion. No need for extreme ultraviolet lithography, the cutting-edge tool that has become synonymous with semiconductor scarcity.
Whether that promise holds up in volume production remains to be seen. The company has run about 2,000 wafers to date, a modest figure for a startup preparing to challenge established memory giants, and has yet to release independent performance benchmarks.
Targeting Two Markets at Once
Kepler is pursuing parallel product lines: a high-speed SRAM replacement for on-chip caches and HBM-class memory designed to sit alongside GPUs. "Now we're making SRAM and HBM in parallel," CEO and cofounder Debo Olaosebikan told Wired. The company's roadmap calls for first HBM samples later this year, with plans for a production ramp in Singapore by 2027 and U.S.-based chip manufacturing starting in 2028.
The dual strategy reflects the urgency investors see in the memory market. Srini Ananth, managing director at Intel Capital, said the firm initially debated whether Kepler should focus on SRAM or HBM first. "We figured the market would dictate that, and now you're seeing a demand for both."
Kepler's website describes the technology as "AI's new memory—beyond HBM & SRAM, without EUV." The company says it aims to approach SRAM bandwidth per watt while delivering HBM-class capacity, all manufactured "in fabs the world already has." That last phrase carries weight in an industry where leading-edge fabrication capacity is measured in months-long waiting lists.
The startup uses 3D-stacking methods to pack memory layers, Wired reported, techniques that are used in advanced memory manufacturing, including by leading firms.
A Material Gamble
At the core of Kepler's technology is a composite ferroelectric material that enables low-voltage memory cells. Cofounder and CTO Sasi Manipatruni, who previously led Intel's FEINMAN Center for logic and memory based on quantum materials, said the team cycled through 35 iterations before settling on the current material class. The exact composition remains undisclosed.
But there's a wrinkle. Ed Kaste, senior vice president of GlobalFoundries' CMOS business, flagged a manufacturing constraint in the Wired interview. "Iron is a tough contaminant," he said. "Kepler's solution has to run on dedicated equipment, or be fully encapsulated." That requirement could add cost and complexity to fab integration, potentially undermining the promise of easy retrofitting. GlobalFoundries, a named investor in the $468 million funding round, serves as the primary manufacturing partner.
Kepler claims it can convert a fab to its process in eight months, compared to a typical 24-month timeline, though that figure has not been independently verified. "Our goal is to take the fabs and architectures already built, and push them to the limits of physics," Olaosebikan said.
A Market Running on Empty
The timing may favor Kepler, assuming its technology works. AI memory supply is effectively sold out for years. SK hynix, which commanded a dominant share of HBM revenue in recent quarters, posted record results earlier this year and said customer demand exceeds supply capabilities. CEO Kwak Noh-jung told Reuters that capacity constraints would persist well beyond 2027. "Demand will remain higher than our supply capacity even beyond 2030," he said.
Micron began volume shipments of HBM4 for NVIDIA's latest platform in recent months. Samsung is advancing HBM-PIM and a 3D memory roadmap it unveiled at Flash Memory Summit in August. TrendForce noted in September that HBM3E remains the dominant standard as HBM4 transitions begin, and that advanced packaging capacity constraints will ease only slightly as TSMC expands its CoWoS capacity by more than 60 percent.
Omdia forecast in July that supply bottlenecks across HBM, advanced packaging, and leading-edge nodes will persist through at least 2027. Gartner projected in August that semiconductor revenue would approach $1.6 trillion, with memory growth supported by AI infrastructure and rising HBM content per server.
The broader picture: data center electricity use surged 17 percent year-over-year in 2025, according to the International Energy Agency, with AI's share growing. Five large tech firms collectively spent more than $400 billion in capital expenditures in 2025, a figure expected to rise 75 percent this year.
Alternative Routes Around the Problem
Kepler is not alone in trying to circumvent the HBM bottleneck. NVIDIA's Groq 3 LPU, announced at GTC in March and detailed by IEEE Spectrum in September, uses hundreds of megabytes of on-chip SRAM to deliver up to 150 terabytes per second of per-chip bandwidth for inference workloads. That approach reduces reliance on HBM during the decode phase.
D-Matrix announced in June that its Corsair platform entered full production for priority customers. The system uses SRAM-based in-memory compute chiplets with LP-DDR5 side memory, explicitly avoiding HBM and CoWoS constraints.
Ferroelectric Memory GmbH, a German startup focused on hafnium-oxide-based ferroelectric devices, raised €100 million in equity and subsidies last year, Bloomberg reported. Academic work at Imec, presented at VLSI in June, demonstrated low-voltage ferroelectric capacitors with endurance around 10 trillion cycles. Researchers also built the first functional five-layer vertical ferroelectric transistor stack, suggesting a feasible path to dense 3D ferroelectric memory.
The ferroelectric approach, in other words, is gaining traction beyond Kepler's walls.
Federal Dollars and Domestic Manufacturing
The NIST letter of intent announced July 29 would provide Kepler up to $245 million "to develop in the U.S. a new class of high-performance AI memory technology enabled by innovative 3D and ferroelectric technologies," according to the Department of Commerce. The same round included up to $300 million for GlobalFoundries to develop co-packaged optics. Letters of intent are conditional; final award amounts may differ after due diligence.
U.S. export controls revised in January explicitly condition advanced AI chip licenses on not diverting global foundry capacity from U.S. customers, according to the Bureau of Industry and Security rule effective January 15. That policy creates additional incentives for alternative memory and manufacturing pathways that add capacity without competing for constrained leading-edge nodes or packaging.
Micron is expanding HBM packaging to U.S. fabs in Idaho, New York, and Virginia as part of its CHIPS Act funding, the company announced when unveiling its Micron Research Labs in March.
Questions That Remain
Kepler's thesis rests on scaling a novel material to volume production. The company has named customers in undisclosed partnerships but has not publicly demonstrated independent benchmarks or provided teardown data. Contamination control remains a question mark. The iron present in the ferroelectric composite requires dedicated equipment or full encapsulation, according to GlobalFoundries, which could limit how quickly existing fabs can integrate the technology.
The startup also faces the challenge of proving its performance claims in a market where incumbents have spent decades optimizing memory architectures. SK hynix, Samsung, and Micron have deep relationships with hyperscalers and established manufacturing at scale. Kepler will need to deliver not just working chips, but chips that justify the risk of switching suppliers.
Still, the company has attracted serious capital and serious partners. Whether that translates into a viable alternative to today's memory hierarchy may become clearer later this year when the first HBM samples are scheduled to emerge. For now, Kepler is betting that the industry's desperation for memory capacity will give an unconventional approach a real shot.
