For years, hardware hackers have had a peculiar problem. They could write code, compile it, synthesize it—take it all the way from high-level Verilog down to a working bitstream. But the actual silicon? That remained stubbornly opaque, locked behind foundry walls and vendor NDAs.
A GitHub repository that surfaced in early April 2026 might change that calculus. Maybe.
The project, called Aegis, bills itself as "Fully open-source FPGA, from the silicon up"—a phrase that sounds almost too ambitious until you start digging through the commits. Unlike the open-source FPGA efforts that came before it (and there have been many), Aegis doesn't just offer tools that work with proprietary chips. It proposes the whole stack: fabric architecture, place-and-route infrastructure, and crucially, a viable path to actual manufactured silicon.
The maintainer, Tristan Ross—who goes by "RossComputerGuy" in developer circles—pushed the initial commits April 1-4. Ross, based in California, has previous contributions scattered across Nix and LLVM projects, the kind of resume that suggests someone comfortable working deep in the technical weeds.
Whether Aegis delivers on its promise remains very much an open question. But the timing tells you something about where the industry is heading.
Manufacturing Gets (Slightly) Less Impossible
Here's the thing about custom silicon: tapeout costs have traditionally kept it in the domain of companies with serious venture backing. That barrier hasn't disappeared exactly, but it's eroding in interesting ways.
Take wafer.space, a pooled manufacturing service that launched after Efabless shut down in early March 2025. The founder, Tim "mithro" Ansell, set up a model where developers share wafer space on GlobalFoundries' GF180MCU process. The economics are still real money—$7,000 gets you 1,000 bare dies, $8,500 if you want them wire-bonded to PCBs—but it's a different proposition than the six-figure minimums that once defined this world.
You can even buy an undiced wafer for $2,000, if you're the sort of person who has use for such a thing.
The first production run set a December 3, 2025 deadline for GDS files, with dies having shipped mid-March. Aegis Terra 1, the project's inaugural device, targets exactly this manufacturing flow.
The specs, documented in the April README, outline what you'd call a modest FPGA. Roughly 2,880 LUT4 elements. 128 BRAM tiles, each 128×8 bits. Sixty-four DSP18 blocks handling 18×18 multiply-accumulate operations. 224 I/O pads, 4 SerDes interfaces, a couple clock tiles, 4 routing tracks per edge.
These numbers don't threaten AMD's Versal Gen 2 or anything Altera's shipping. But that's rather beside the point. Competition with established vendors isn't what this is about—not really.
Open Means Open This Time
The FPGA community has been chipping away at proprietary barriers for the better part of a decade, though progress has been fragmented.
Project IceStorm reverse-engineered Lattice's iCE40 bitstreams starting in 2015. Project Apicula did similar detective work on Gowin FPGAs. YosysHQ built synthesis and place-and-route tools that work across multiple architectures—a genuine accomplishment. Cologne Chip released GateMate with a fully open toolchain. Even radiation-hardened space-grade devices got open support; YosysHQ completed work on NanoXplore's FPGAs by late 2024.
Impressive efforts, all of them. But they shared a fundamental limitation: they worked around proprietary silicon. The underlying hardware remained a black box, even if the tools weren't.
Aegis attempts something different. The fabric architecture sits in the open. The toolchain—Yosys for synthesis, nextpnr for place-and-route using the viaduct backend (according to an early April commit), plus custom packer and simulator—open. The RTL-to-GDS conversion relies on OpenROAD. Even the process design kit, GF180MCU, is open, a collaboration between Google and GlobalFoundries.
A developer on Reddit's r/FPGA forum noted in early April that Aegis emphasizes an integrated, end-to-end pipeline with verification, using Nix for reproducible builds and ROHD for rapid iteration. The maintainer suggested this approach enables faster generation cycles compared to frameworks like FABulous or OpenFPGA—both legitimate open-source FPGA generators, just with different architectural philosophies.
Whether that claim holds up under scrutiny is, well, something we'll only know once people actually use it.
The Wider Movement
Aegis doesn't exist in isolation, of course. The open silicon movement has been building momentum, especially around security-critical applications where transparency matters more than raw performance.
OpenTitan—a collaborative root-of-trust project between Google and lowRISC—reached commercial availability in February 2024. LowRISC CEO Dr. Gavin Ferris called it "the first open-source silicon project to reach commercial availability," which might be promotional speak but isn't necessarily wrong. By March of this year, Chromebooks were reportedly shipping with OpenTitan chips inside.
ZeroRISC, a startup commercializing OpenTitan-based products, closed a $10 million seed round in mid-2025. CEO Dominic Rizzo's comment at the time captured the prevailing sentiment: "Open-source silicon is becoming an inevitability with the adoption of implementations like OpenTitan by Google."
The CHIPS Alliance laid out its priorities for this year back in February, explicitly including AI/ML for EDA and continued F4PGA development. Industry backing for open FPGA and silicon tooling appears to be growing, though "appears" is doing some heavy lifting there—industry backing can evaporate quickly when market conditions shift.
Policy is playing a role too, perhaps more than is immediately obvious. The U.S. CHIPS Act has funneled significant funding toward domestic manufacturing—GlobalFoundries received up to $1.5 billion announced in February 2024, while SkyWater got up to $16 million by late 2024, with disbursements continuing into 2026. Total announced grants and loans have run into the tens of billions across dozens of projects, though tracking the actual disbursements versus announcements gets murky.
Europe is moving along similar lines. The EU cleared €623 million in German state aid for GlobalFoundries Dresden and X-FAB Erfurt in early January. By late March, the European Commission was signaling a forthcoming "Chips Act 2.0" with references to an "Open EU Foundries" concept—bureaucratic language that may or may not translate into actual policy.
These policies matter because they strengthen the manufacturing ecosystem that projects like Aegis depend on. Without accessible foundries, open silicon designs remain theoretical exercises.
The Market Reality
Pinning down the FPGA market with precision is harder than you'd think. Syndicated research reports offer wildly different numbers depending on methodology and who's paying for the analysis.
Precedence Research estimated the market around $11.52 billion in 2026, growing to $27.43 billion by 2035—roughly 10.1% CAGR. Microchip USA's infographic put it at $11.02 billion this year, reaching $17.23 billion by 2031, closer to 9.35% CAGR. The ranges vary, but the trajectory is consistent: growth, driven by edge computing, AI inference, and SmartNIC applications.
The traditional players remain overwhelmingly dominant. AMD, which acquired Xilinx, continues scaling its portfolio—Spartan UltraScale+ for cost-optimized edge applications, Kintex UltraScale+ Gen 2 for mid-range workloads, and Versal Gen 2 for high-end AI, with silicon samples arriving earlier this year.
Altera re-emerged as an independent company after Intel divested in the latter half of 2025, retaining a 49% stake but making Altera the largest pure-play FPGA vendor again—a title that carries both prestige and pressure. Lattice Semiconductor reported what it called record communications and computing revenue for 2025, announced in March, though specific figures weren't disclosed in the press materials.
Smaller players carve out niches. Efinix expanded its Titanium family targeting AI workloads with MIPI and LPDDR support. QuickLogic maintains its open-source toolchain and posted fiscal 2025 results in early March. Cologne Chip's GateMate, with its fully open toolchain, has attracted hobbyist and educational adoption—Olimex's GateMateA1-EVB board makes it reasonably accessible for tinkerers.
Aegis isn't competing with any of these directly. Terra 1's 2,880 LUTs wouldn't replace a Spartan, much less a Versal. It occupies different territory entirely.
Educational use. Research projects. Low-volume specialized applications. Scenarios where complete transparency matters more than raw performance. That's the market Aegis is aiming for, assuming it gets that far.
The Hard Part
Aegis is very new. The commits only appeared a few weeks ago. The specifications in the README should be considered aspirational rather than final—documentation written before silicon has a tendency to evolve once reality intervenes.
Getting from architecture definition to working silicon involves countless unglamorous details. Timing closure. Power analysis. Design rule checking. Verification at every level, then more verification. The wafer.space manufacturing model provides a predictable path to tapeout, which helps, but there's a substantial gap between "we have GDS files" and "we have tested, working chips that behave as specified."
That gap is where many ambitious silicon projects stall, quietly and without much fanfare.
The Reddit discussion in early April mentioned plans for crowdfunding development boards and community tapeouts. Whether that materializes depends on hitting verification and timing milestones first. The $7,000 price point for 1,000 dies is accessible compared to traditional fab costs, certainly, but it's still significant money for an unproven architecture with no track record.
Export controls add another wrinkle. The U.S. Bureau of Industry and Security strengthened restrictions on advanced computing semiconductors in early 2025, with additional EDA tool limits rolling out between May and July. While these rules primarily target advanced nodes and AI accelerators, supply-chain compliance affects the broader ecosystem in ways that aren't always immediately apparent. Open-source projects aren't magically immune to these dynamics, however much we might wish otherwise.
What This Opens Up (Maybe)
The promise of Aegis—and projects like it—isn't about displacing AMD or Altera. It's about expanding what's possible at the margins of the market.
Academic researchers could design custom FPGA architectures tailored to specific problems, tape them out, and test them at what passes for reasonable cost in this world. Startups building niche hardware products could optimize fabric designs for their exact use case rather than adapting off-the-shelf parts that weren't designed with their application in mind. Security-conscious applications could benefit from complete visibility into the silicon—no proprietary bitstream formats, no undocumented features, no hidden logic that might or might not be doing something you didn't authorize.
The educational value is harder to quantify but potentially significant. Students typically learn FPGA development on black-box chips with vendor-specific tools. They get results, but they don't necessarily understand what's happening under the hood. An open architecture lets them see how the fabric actually works—how LUT configurations map to silicon, how routing resources connect, how timing constraints propagate through the design.
That kind of transparency, in theory, makes better engineers. Whether it does in practice depends on curriculum design and teaching quality, but at least the possibility exists.
Recent research has explored using FPGAs for edge AI applications—CNN acceleration with MLIR frameworks, graph neural networks on SoC FPGAs, bit-width-aware few-shot learning on PYNQ platforms. Embedded FPGA (eFPGA) fabrics within SoCs have shown promise for balancing flexibility and efficiency; one study found that an eFPGA hybrid retained roughly 90% of ASIC performance with notable power benefits. These application areas don't necessarily require the largest, fastest FPGAs—they need appropriate sizing, good power characteristics, and often the ability to customize or deeply understand the fabric.
FABulous, an open-source eFPGA generator that predates Aegis, has already achieved multiple silicon-proven tapeouts across various process nodes including GF180MCU. OpenFPGA provides another framework for FPGA architecture generation, with documentation that's been actively maintained. The ecosystem of open FPGA generators is growing. Aegis adds to it rather than replacing anything—which may ultimately be the healthiest outcome.
What Happens Next
Whether Aegis itself succeeds matters less than the broader trajectory it represents.
Open PDKs like GF180MCU and Sky130 exist now. Pooled manufacturing services like wafer.space make tapeout accessible—not cheap exactly, but accessible in a way it wasn't five years ago. Toolchains like Yosys and nextpnr mature steadily, if not always smoothly. The pieces are aligning for more experiments in open silicon, though experiments and production-ready products remain very different things.
The maintainer's focus on integrated pipeline and verification suggests an understanding that "open" isn't enough—the tools need to actually work reliably, reproducibly, without mysterious failures that eat weeks of debugging time. The Nix-based build system aims for reproducibility, which matters more than it might sound. The migration to nextpnr's viaduct backend, documented in early April commits, shows active development rather than a static snapshot.
The biggest question is community uptake.
Open hardware projects need more than code in a repository. They need users willing to test, document bugs, contribute improvements, and build actual products. The r/FPGA discussion showed interest, which is encouraging, but interest and sustained contribution are fundamentally different things. Many open hardware projects generate initial enthusiasm and then fade as contributors move on to other priorities.
If Aegis reaches the point of working silicon and stable toolchains—and that's a meaningful "if"—it could seed a new category of custom FPGA development. Not replacing commercial FPGAs. Not competing on performance or gate count. But enabling projects that couldn't justify closed-source licensing or needed transparency above all else.
Small batch runs. Specialized architectures. Research vehicles. Educational tools. The applications that live in the long tail of the market, too small or too weird for major vendors to bother with.
The semiconductor industry has historically kept innovation locked behind proprietary walls for what are, to be fair, good reasons. Building chips is extraordinarily complex and expensive. The failure rate is high. Proprietary control helps manage risk and protect investment.
But those walls also limit what's possible. They restrict experimentation. They make certain classes of projects economically unviable, not because they couldn't work technically but because the licensing and NDA requirements add too much overhead.
The open silicon movement, piece by piece, is finding ways around those walls. Aegis represents one more piece—perhaps a small one, perhaps an important one. It's hard to say yet. The commits are barely a month old.
Either way, it's there now. In the open. Ready for anyone to build on, modify, or learn from.
What happens next depends on whether anyone does.
