Two engineers in San Francisco think they've found a way to shave days off the most tedious part of chip design. Hardware Intelligence, fresh out of Y Combinator, released a pair of tools this summer that promise to compress and automate what semiconductor companies spend the most time on: figuring out why their simulations fail.
The startup is hardly bashful about its ambitions. "We're picking a fight with a $20B industry," reads the landing page for Wave, one of the products, calling out Synopsys, Cadence, and Siemens by name. Those three giants dominate electronic design automation, the software layer that makes modern chip development possible. Hardware Intelligence is betting that even a small efficiency gain in verification—the painstaking process of checking that a chip design works—could resonate across an industry that runs tens of millions of simulation jobs every week.
The bottleneck is well documented. A 2018 study by Siemens found that verification eats up more than half of chip development time, with debugging alone accounting for 44% of that effort. The central frustration, according to Hardware Intelligence, is straightforward: when a test fails, engineers often have to rerun the entire simulation with diagnostic logging turned on, then wait hours or sometimes days to see what went wrong. It's a cycle that compounds across large teams and complex designs.
Wave, which launched in July, attempts to short-circuit that loop. The tool runs locally over SSH and leans on customers' own language model endpoints to trace failures, suggest fixes, rerun tests, and compare waveforms without manual intervention. Hardware Intelligence says the agent integrates with existing simulation workflows and keeps all data on-premises. It handles standard formats like VCD and FST natively, with support for FSDB available on request.
The second product, WaveZip, tackles the file size problem. Traditional waveform dumps can balloon to several gigabytes for a single test run, and turning them on slows simulations by a factor of three to eight, depending on the design. WaveZip, released in August, is a compressed format written in pure SystemVerilog that the company claims records every run with overhead between 3.3% and 8.6%. Hardware Intelligence tested it against four open RISC-V cores using Verilator. In one case, a test that generated a nearly 3 GB file with standard FST format produced a 5.4 MB WaveZip file instead, a reduction of more than 500x. Other designs compressed between 25x and 398x smaller, all without losing data.
Opening those compressed files also proved faster than simply rerunning the simulation with dumps enabled. The startup measured unzip times at seven to thirteen times quicker than a full rerun across the test cases. That matters at scale. ARM, for instance, runs upwards of 53 million EDA jobs per week on AWS, sometimes hitting 9 million in a single day and scaling to 350,000 vCPUs, according to an AWS case study. Even small runtime penalties multiply quickly under those conditions.
The incumbents aren't standing still. Synopsys announced a 1.5x simulation speedup and a fivefold reduction in FSDB file sizes with dynamic aliasing in Verdi earlier this year, and Cadence launched its ChipStack AI Super Agent around the same time, with partner Altera reporting roughly 10x reductions in some verification workflows. Synopsys and Microsoft demonstrated an autonomous debug system at the Design Automation Conference in August. A handful of other YC-backed startups are building AI-native chip tooling as well, including Silimate, SiLogy, and SigmanticAI, alongside independent ventures like Bronco AI, Cogita EDA, and LogikBee.
Athreya Anand, Hardware Intelligence's co-founder and CEO, previously worked as a tech lead at Google on agentic workflow tools and prediction models for GV, according to his YC profile. Before that, he was at Tesla and Amazon on the AWS Inferentia team. He holds a master's in machine learning and AI from Georgia Tech. His co-founder, Rishov Sarkar, recently completed a PhD in electrical and computer engineering at Georgia Tech focused on chip simulation and compilers. Sarkar's background includes work on AMD's AI Engine simulators and LLVM-based tools at Siemens EDA, the YC directory notes.
The two-person team is looking for design partners and pilot customers, though the company hasn't publicly named any users yet. Team Ignite Ventures disclosed an investment in Hardware Intelligence in September, noting that the firm backed 17 companies in YC's recent cohort. Hardware Intelligence declined to share funding figures.
The broader computer-aided engineering market, which includes simulation software, has been growing steadily. Revenue in the category topped $2 billion in the first quarter of this year, up more than 15% from the prior year, according to the ESD Alliance. Whether a two-person startup can carve out meaningful share against entrenched players with decades of customer relationships remains an open question. But in an industry where engineers routinely lose afternoons waiting for simulations to finish, the pitch is simple: what if you didn't have to wait at all?
