The electricity meter at a modern AI data center spins like a slot machine. Every terabyte of inference—the unglamorous work of running trained models—carries a hidden cost measured not in dollars but megawatts. And the bill, as they say, is coming due.
By 2030, data centers worldwide will consume roughly 945 terawatt-hours annually. That's double today's draw, according to the International Energy Agency, and AI-optimized facilities will quadruple their appetite in that same window. For infrastructure operators watching power budgets spiral upward like a rocket trajectory, the question has shifted. It's no longer whether to seek alternatives to copper-and-silicon but how fast they can deploy them.
Which brings us to light—and to a small band of chip designers convinced that photons and analog mathematics can break the energy curve before it breaks the industry.
Singapore-based OptoML closed a $1.8 million pre-Series A round in February 2026 from Bluehill.VC and A99. The startup represents a particularly audacious synthesis: analog in-memory compute fused with integrated optical interconnects. Its pitch? A FinFET-based system-on-chip delivering up to 50 times the energy efficiency of conventional digital accelerators. If validated in production silicon—still a big "if"—that figure would rewrite data center economics overnight. OptoML has already taped out a 12-nanometer test chip at TSMC and partnered with India's Kaynes Semicon for backend assembly. Whitepapers, in other words, are giving way to actual chips.
The company is hardly alone. Across the semiconductor ecosystem, optical interconnects and compute-in-memory architectures—technologies once confined to university labs—are attracting hundreds of millions in venture capital and acquisition interest. What's less clear is whether this convergence arrives in time to prevent AI infrastructure from outrunning the available grid.
When Physics Meets PowerPoint
Data center capacity is on a collision course with reality. McKinsey projects global capacity will surge from 82 gigawatts in 2025 to 219 gigawatts by 2030, with AI workloads claiming roughly 156 gigawatts of that total. Cumulative capital expenditure to build this out could reach $6.7 trillion by decade's end, much of it concentrated in the United States and China, which together account for roughly 80 percent of projected growth.
Here's the wrinkle: inference is rising faster than training. That intensifies pressure on per-watt efficiency rather than raw peak performance. You can't just throw more silicon at the problem; you have to make every electron count.
Optical interconnects are having a moment. The market for optical links inside AI data centers was valued at approximately $9.94 billion in 2025 and is forecast to hit $31.0 billion by 2033—a compound annual growth rate near 15.3 percent. Silicon photonics, the enabling technology, is growing even faster: from $1.9 billion in 2024 to an estimated $8.5 billion by 2033. Co-packaged optics—integrating photonic I/O directly onto chip packages—remains nascent at $84 million in 2024, but analysts project a blistering 49 percent CAGR to $3.1 billion by 2033.
Shipment data tells the story. In 2025, 800-gigabit-per-second optics doubled year-over-year. 1.6-terabit modules entered volume production at select hyperscalers. Industry tracker TrendForce expects 800G-and-above transceiver shipments to multiply 2.6 times by 2026. Optical transport equipment revenue climbed 10 percent to $16 billion in 2025, with cloud providers' direct purchases of wavelength-division multiplexing gear for data center interconnect surging roughly 50 percent.
The infrastructure, in short, is being built in real time. The question is whether it's being built fast enough.
Yet optical links alone don't solve the compute bottleneck. Traditional digital accelerators shuttle data between memory and processing units across copper traces, burning energy with every movement—a problem engineers call the von Neumann bottleneck, after the computer architecture that created it. Analog in-memory compute attacks this by performing calculations directly within memory arrays, collapsing data movement. IBM Research demonstrated 14-nanometer phase-change memory chips achieving near-software accuracy on deep neural networks, with kernelized attention mechanisms for transformers showing less than 1 percent accuracy loss.
These aren't lab curiosities anymore. They're engineering prototypes inching toward commercialization, perhaps faster than the founders expected.
Three Forces, One Conclusion
Three interrelated pressures are accelerating the shift toward optical and analog solutions: bandwidth saturation, thermal limits, and regulatory tightening.
Bandwidth first. IEEE Communications Society researchers note that current 100-gigabit PAM4 optics consume around 20 picojoules per bit. To scale AI fabrics toward the million-GPU "AI factories" that Nvidia envisions, energy per bit must drop to 5 picojoules or lower. Copper SerDes can't reach those figures at multi-terabit aggregate speeds without prohibitive power envelopes.
Co-packaged optics, by contrast, eliminate the electrical-to-optical conversion overhead of pluggable modules and slash latency. Ayar Labs' TeraPHY optical chiplet delivers 8 terabits per second bidirectional throughput with roughly 10 nanoseconds of added latency, reaching millimeter-to-kilometer distances while remaining UCIe-compliant for chiplet integration. Intel demonstrated a fully integrated optical compute interconnect chiplet co-packaged with a CPU in 2024, achieving 4 terabits per second with on-chip lasers and amplifiers. The industry, in other words, isn't just talking about this stuff.
Heat compounds the problem. As chips push beyond 1,000 watts per package, traditional air cooling falters. Data center operators are deploying liquid cooling and exploring immersion tanks, but power density remains a gating factor for rack design. Analog in-memory compute reduces data movement, which in turn lowers heat generation. Startups like Mythic AI—which raised $125 million in December 2025 after a restructuring that nearly killed the company—claim their analog flash-based processors can deliver 100-times energy advantages over digital GPUs for inference workloads. d-Matrix, which secured $275 million in November 2025, is pursuing digital in-memory compute with 3D-stacked memory to displace high-bandwidth memory in inference accelerators.
Both approaches aim to keep compute power budgets within manageable thermal envelopes. Whether they succeed is another story.
Regulatory tailwinds are less visible but equally significant. The European Union's Energy Efficiency Directive mandates annual energy reporting from data centers starting in September 2024, with a sustainability rating scheme and minimum performance standards expected by March 2026. In the United Kingdom, grid regulator Ofgem warned in February 2026 that proposed data center projects could exceed 50 gigawatts, potentially doubling national electricity demand.
Policy responses are tightening grid connection criteria. Data center developers face higher hurdles to secure power allocation. In the United States, the CHIPS and Science Act is channeling $1.4 billion into advanced packaging R&D through the National Advanced Packaging Manufacturing Program, with a separate $1.6 billion notice of funding opportunity for packaging innovation. GlobalFoundries is building a $575 million silicon photonics packaging and testing center in New York. Amkor broke ground on an advanced outsourced assembly and test facility in Arizona expected to enter production around 2028.
The policy and infrastructure buildout converge on a singular message: the industry is betting billions that photonics and memory-centric compute will become standard architectures within a few years. The alternative—running out of grid capacity—is unthinkable.
From Vision to Silicon
Nvidia's Million-GPU Gambit
Nvidia announced its Spectrum-X and Quantum-X photonics switches in 2025, co-packaged optics platforms explicitly designed to scale AI clusters to millions of GPUs. CEO Jensen Huang framed switch-integrated photonics as a necessity, not an option, citing efficiency and network resiliency improvements. The switches support 1.6-terabit-per-second port configurations and leverage partnerships with TSMC, Coherent, Corning, and Lumentum for lasers, photonic engines, and fiber assemblies.
Nvidia's roadmap effectively validates CPO as a near-term production technology, not a distant research program. When the company that controls roughly 80 percent of the AI accelerator market makes that bet, the rest of the industry tends to follow.
Lightmatter's Photonic Bet
Boston-based Lightmatter raised $400 million in October 2024 and has since unveiled a collaboration with Synopsys to integrate 224-gigabit SerDes and UCIe interfaces into its Passage co-packaged optics platform at the 3-nanometer node. Lightmatter joined the UALink Consortium in December 2024, aligning its photonic interposer with the open accelerator interconnect standard being developed by AMD, Intel, Google, Microsoft, and others. The company's L200 CPO module targets 32 to 64 terabits per second aggregate bandwidth, and reference platforms are shipping in 2025 for customer evaluation.
Lightmatter's pitch centers on eliminating GPU idle time in enterprise AI data centers—photonic I/O keeps accelerators fed with data, reducing the memory-bandwidth stalls that plague training and inference jobs. It's a compelling story, assuming the hardware holds up in production.
TSMC Opens the Gates
Taiwan Semiconductor Manufacturing Company formalized its Co-Packaged Optics Using Photonic Engines framework to provide turnkey optical subsystems for chiplet designs. In early 2025, design services firm Alchip and optical I/O specialist Ayar Labs demonstrated the industry's first COUPE-based optical connectivity module, targeting up to 100 terabits per second per AI accelerator package. The module integrates an electrical IC and photonic IC with UCIe-compliant die-to-die links.
This matters. A lot. It lowers the barrier for smaller chip developers to adopt optical I/O without developing their own photonics—democratizing access to a technology previously reserved for hyperscale budgets.
OptoML's High-Wire Act
OptoML, founded in 2024 by Saravana Maruthamuthu—a semiconductor veteran with stints at Infineon, Intel, and Qualcomm—embodies the convergence thesis. The startup is building a heterogeneous SoC that pairs an analog in-memory compute neural processing unit with RISC-V or ARM CPUs and GPU cores, all tied together via integrated optical links. Its roadmap includes an MVP demonstrated on a 130-nanometer process running MNIST digit recognition, followed by FinFET test chips and the 12-nanometer TSMC tape-out announced with its February 2026 funding.
Bluehill.VC, one of the lead investors, explicitly cited the combination of analog compute and optical interconnects as a hedge against the bandwidth, latency, and energy bottlenecks plaguing current architectures.
The company's 50-times efficiency claim remains unvalidated in production silicon. But the underlying logic is sound: analog matrix multiplication eliminates the energy overhead of digital arithmetic units and memory fetches, while optical interconnects sidestep the power consumption of high-speed electrical SerDes. If OptoML can prove reliability—a perennial concern with analog circuits prone to process variation and thermal drift—it could carve out a niche in edge-to-on-premises inference deployments where power budgets are tightly constrained.
That's a big "if."
d-Matrix and the Digital Alternative
Not all memory-centric compute is analog. d-Matrix is pursuing a digital approach with 3D in-memory compute, aiming to displace high-bandwidth memory in inference accelerators. The company's $275 million Series C in November 2025 signals investor confidence that digital in-memory architectures can deliver order-of-magnitude efficiency gains while maintaining the precision and programmability of conventional digital designs. d-Matrix claims 10-times speed and 10-times efficiency improvements over HBM-based systems, positioning 3DIMC as a drop-in alternative for inference clusters.
Mythic's Near-Death Revival
Mythic AI, which nearly shuttered before securing $125 million in December 2025, is another analog compute-in-memory pioneer. Using analog flash memory arrays, Mythic claims 100-times energy advantages for inference workloads. The company is targeting both edge devices and data center analog processing units.
Its revival suggests that investors believe analog techniques have a viable path to market, despite earlier setbacks around manufacturing yields and accuracy trade-offs. Or perhaps they're just betting that someone in the analog space will break through, and Mythic's team has the scars to prove they know what doesn't work.
The Foundry Bottleneck Loosens
On the supply side, GlobalFoundries acquired Advanced Micro Foundry to become the world's largest pure-play silicon photonics foundry. GF's Fotonix platform supports monolithic integration of photonics on 300-millimeter wafers, with public endorsements from Nvidia and Cisco. This acquisition expands the photonics production pipeline, addressing a bottleneck that has historically limited CPO adoption.
Foundry capacity is critical. Without it, startups like OptoML face long lead times and high costs for test chips and pilot runs. GlobalFoundries' move signals that the supply chain is starting to align with demand. Starting to.
The Road From Here
Multiple credible roadmaps—from Nvidia, Intel, Ayar Labs, Lightmatter, and Ranovus—indicate that co-packaged optics will enter volume production for AI scale-up fabrics between 2026 and 2028. Pluggable optics will remain dominant in the near term, with 1.6-terabit modules becoming mainstream in 2026 and 2027 as costs per gigabit decline toward 50 cents by 2027. Some analysts expect full CPO deployments within five to six years once serviceability and reliability concerns are resolved.
The DARPA PIPES program, active since 2020, has targeted greater than 100 terabits per second per package at less than 1 picojoule per bit—benchmarks that suggest government and industry are aligned on the destination, if not the exact route.
Open interconnect standards are accelerating adoption. The UALink Consortium released its 200-gigabit 1.0 specification in April 2025, providing an open alternative to Nvidia's proprietary NVLink for accelerator-to-accelerator communication across up to 1,024 nodes per pod. The Ultra Ethernet Consortium launched its 1.0 specification for AI and HPC-scale Ethernet, with Broadcom shipping an 800-gigabit Thor Ultra NIC aligned to the spec.
These standards create multi-vendor ecosystems that reduce lock-in and drive competition, which historically accelerates deployment curves. History doesn't always repeat, of course, but it often rhymes.
Analog and digital in-memory compute are moving from research to engineering. IBM's demonstrations with phase-change memory crossbars show that kernelized attention for transformers can run on analog hardware with minimal accuracy loss. Startups like Mythic and d-Matrix have raised hundreds of millions to commercialize memory-centric designs for inference. The fundamental bet is that moving computation to where data resides—rather than shuttling data to computation—unlocks a step-function improvement in efficiency.
If that bet pays off, heterogeneous systems combining analog NPUs, digital CPUs, and optical interconnects could become the default architecture for inference clusters by the end of the decade.
Perhaps the most telling signal is consolidation. Marvell's pending $3.25 billion acquisition of Celestial AI, announced in December 2025, underscores that photonic fabric technology is no longer speculative. When a major semiconductor company writes a check that size, it reflects conviction that the market is entering a growth phase. Similarly, private capital inflows—Lightmatter's $400 million, d-Matrix's $275 million, Mythic's $125 million, and even Optalysys's £23 million raise in January 2026 for photonic computing—suggest that investors see optical and memory-centric architectures as necessary infrastructure for the AI era.
The money, in other words, is starting to follow the PowerPoint.
For data center operators and CTOs evaluating next-generation platforms, the calculus is shifting. The question is no longer whether optical interconnects and compute-in-memory will displace copper and von Neumann architectures. It's which vendors will deliver production-ready systems first, and at what cost. OptoML's approach—fusing analog compute with optical I/O in a single SoC—is aggressive. Perhaps risky. But it reflects a broader recognition that incremental improvements won't close the gap between AI's appetite for bandwidth and power and the physical limits of electrons crawling through copper.
The highway is being paved with light. Whether it gets built fast enough to avert an energy crisis is the trillion-dollar question—and the answer is being written in silicon, one tape-out at a time.
