Three engineers think they've cracked one of the hardest problems in AI hardware. Maybe they have.
Baud, a San Francisco startup barely out of Y Combinator's incubator, is betting everything on a chip design that does away with multiplication—the fundamental operation behind nearly every AI accelerator shipping today. Instead of the multiply-accumulate cores that power everything from NVIDIA's GPUs to Google's TPUs, Baud claims to have built a novel ASIC architecture, though the company hasn't disclosed the specific details of how it sidesteps matrix multiplication. If they're right, they could reshape how the industry thinks about training large models. If they're wrong, well, the graveyard of ambitious chip startups is already crowded.
In early July, the team posted a live demo: a 50-million-parameter language model running inference north of 1,000 tokens per second on a single FPGA meant to emulate their eventual silicon. The model—trained on a dataset called SimpleStories from Hugging Face—makes mistakes, which Baud acknowledges freely. But for a company that's existed only a few months, the fact that anything runs at all is worth noting. According to the company's YC launch materials, the design has already been validated on GlobalFoundries' 12-nanometer process. Tape-out, the make-or-break moment when a chip design gets sent to fabrication, is scheduled for the end of 2026.
Rethinking arithmetic at the silicon level
Baud's pitch hinges on what it calls "orders of magnitude better performance" compared to existing chips. Traditional AI accelerators lean hard on matrix multiplications, the computational engine underneath transformer models and neural networks. Exactly how Baud avoids this hasn't been disclosed—the company is keeping the technical specifics close. What's known: they've built a compiler stack to translate existing models onto their hardware, and they're recruiting design partners who get reserved capacity on the first cluster in exchange for early feedback and reality checks.
No design partners have been named publicly. That could mean traction is still early, or it could mean the usual NDAs are in force.
The pedigree
The founding team has the kind of résumés that make investors pause. CEO Sarang Zambare is a multi-time founder with four patents and more than seven years working in deep learning and AI hardware. He led machine learning for Peloton's Guide product—a project that went from concept to over 100,000 devices in the field. Before that, he was a founding ML engineer at Caper, the smart-cart company that Instacart acquired in late 2021.
Eric Taylor, Baud's chief hardware architect, brings a decade of ASIC design experience: four tape-outs, two major IP releases, and stints at NVIDIA, Freescale (which became NXP), Arteris IP, and most recently Enfabrica. The combination is notable—Zambare understands how models behave in production, Taylor knows how to translate that into silicon. It's broader coverage of the stack than many chip ventures manage early on.
There's an odd wrinkle, though. Baud's legal entity appears to be Cerelyze, Inc., a name that appeared in YC's Summer 2023 batch attached to a tool for converting research papers into executable code. The connection between Cerelyze, Inc. and Baud is inferred but hasn't been officially confirmed by the company. The company is currently listed at three people in YC's directory, with Diana Hu as the primary partner.
What's been built
Beyond the live demo, Baud has made its FPGA-based emulation available for outside experimentation. The demo site says the model was trained on five million tokens and runs at 125 MHz on a U200 FPGA. This is effectively a proof-of-concept meant to validate the architecture before committing to the expense and risk of actual silicon fabrication.
Funding details are sparse. No external investment has been disclosed beyond the standard YC investment—$500,000 under the 2026 deal structure, split between $125,000 for 7% equity on a post-money SAFE and $375,000 on an uncapped most-favored-nation SAFE.
Where this fits
Baud is part of Y Combinator's Summer 2026 cohort, which wraps with Demo Day on September 10, 2026. The batch reflects YC's ongoing fascination with AI infrastructure and custom silicon—themes the accelerator has emphasized in recent Requests for Startups. Other companies in the same cohort include hardware intelligence, working on agentic chip design tools, and Parasma, which is exploring biological neurons for compute.
The AI chip market is brutal. NVIDIA still commands the high ground, and the list of well-funded challengers—Groq, Cerebras, Graphcore, and a dozen others—keeps growing. Most are competing on specialized architectures or novel interconnects. Baud's multiplication-free approach would be a genuine departure if it scales. But the operative word is "if."
The company's performance claims remain unverified by independent benchmarks. The FPGA emulation is promising, but FPGAs and ASICs don't always behave the same way once you're dealing with power, heat, and real-world workloads. Much depends on whether the chip performs as projected when it actually exists.
For now, Baud has a working prototype, a credible team, and a thesis that—if nothing else—is bold enough to get attention. The next twelve months will show whether they've actually solved something, or just built a very clever demo. In the chip business, that distinction tends to reveal itself quickly.
