The machines that make the world's most advanced semiconductors cost upward of $200 million apiece, weigh as much as a commercial airliner, and take years to install. Now they're about to get significantly faster.
ASML, the Dutch company with an effective monopoly on extreme ultraviolet lithography systems, has validated a 1,000-watt EUV light source—a 67% power jump that could reshape the economics of chipmaking at precisely the moment artificial intelligence demand threatens to overwhelm manufacturing capacity. The breakthrough, disclosed to Reuters in February 2026, targets a 50% throughput increase by decade's end.
"This is not a parlor trick," Michael Purvis, ASML's lead technologist for EUV sources, told the news agency. His colleague Teun van Gogh, executive vice president for the company's NXE product line, outlined plans to push each lithography system from roughly 220 wafers per hour today to 330 by 2030. For an industry where capacity additions require multi-billion-dollar investments and half-decade lead times, that productivity gain matters. A lot.
The Physics of Pushing Limits
Getting to 1,000 watts required ASML's engineers to attack the problem from two directions simultaneously. First, they doubled the rate at which microscopic tin droplets feed into the plasma chamber—now running at approximately 100 kilohertz. Second, they refined how those droplets are shaped before vaporization.
The technique hinges on a dual-pulse laser approach: a pre-pulse reshapes each droplet into optimal geometry, then a main pulse from a high-power carbon dioxide laser blasts it into plasma that emits extreme ultraviolet light at 13.5 nanometers. It's elegant in principle. Fiendishly difficult in execution.
Current flagship Low-NA systems, such as the NXE:3800E, handle source powers in the 500- to 600-watt range. Reaching 1,000 watts demanded advances in TRUMPF's drive lasers and tighter droplet timing control, according to technical presentations at industry conferences. Zeiss, which supplies ASML's projection optics, has separately detailed the thermal and aberration challenges inherent in channeling that much power through mirror stacks weighing tons while maintaining nanometer-level precision.
Independent trade publication Bits & Chips noted the proof-of-concept suggests source power may no longer be the limiting factor—provided pellicles, photoresists, wafer stages, and reticle handling can keep pace. Ultimate throughput could reach 400 to 500 wafers per hour long-term, though that remains firmly in the realm of speculation.
Why Throughput Translates to Billions
The immediate target of 330 wafers per hour by 2030 carries real financial weight. Each chip produced on these tools carries a multi-thousand-dollar price tag; higher throughput directly lowers effective cost per wafer. That eases pressure on chipmakers simultaneously grappling with exponential AI infrastructure demand.
ASML reported €32.7 billion in revenue and €9.6 billion in net profit for 2025, with record order books driven by EUV systems. The company expects EUV sales to climb further in 2026, fueled by what CEO Christophe Fouquet described at the November 2024 Investor Day as double-digit compound annual growth in EUV capital spending through 2030.
The backdrop is stark. WSTS forecasts the global semiconductor market will approach $975 billion in 2026, up from $772 billion in 2025, with logic and memory segments—both heavy EUV consumers—leading growth. SEMI, the industry trade group, projects wafer fab equipment spending will hit $122.1 billion in 2026, up from $110.8 billion in 2025. Much of that investment flows toward advanced-node capacity, where EUV lithography is unavoidable.
Jensen Huang, Nvidia's CEO, has characterized AI as "the largest infrastructure buildout in human history," requiring trillions in capital expenditure. That narrative, whether hyperbolic or not, underpins sustained demand for the most productive lithography tools available.
Intel and TSMC Chart Different Courses
The industry's largest foundries are taking divergent approaches to EUV's next chapter. Intel installed the first commercial High-NA EUV system—ASML's EXE:5200B, which achieves 8-nanometer resolution versus 13 nanometers for conventional Low-NA tools—and is positioning its 14A process node to use High-NA on critical layers. The company's CFO confirmed 14A will be more expensive than 18A due to High-NA adoption, though the node promises 15% to 20% better performance per watt or 25% to 35% lower power consumption.
TSMC, which commands more than half the global EUV installed base, has taken a more measured stance. The Taiwanese giant publicly stated it will not use High-NA for its A16 or A14 nodes (1.6-nanometer and 1.4-nanometer class processes). Instead, TSMC is optimizing Low-NA systems with multipatterning techniques and an energy reduction program that cuts peak EUV tool power consumption by 44%—saving an estimated 190 gigawatt-hours by 2030.
Kevin Zhang, a senior TSMC executive, told industry audiences the company will adopt High-NA when return on investment is demonstrable. It's a position that reflects TSMC's legendary capital discipline, but also leaves the door open.
SK hynix, meanwhile, has installed a High-NA system at its M16 DRAM fab in Icheon for next-generation memory research. Samsung is ramping 14-nanometer EUV DRAM production using five EUV layers on Low-NA tools. Reports indicate SK hynix plans to roughly double its EUV fleet by 2027, adding approximately 20 tools to support DRAM and high-bandwidth memory roadmaps critical for AI accelerators.
The Ecosystem Problem
Achieving 1,000 watts in the lab is one thing. Sustaining it in high-volume manufacturing is another entirely.
Pellicles—the thin protective membranes that shield photomasks from contamination—must withstand the thermal load of higher source powers without degrading or absorbing excessive light. Imec, Europe's leading semiconductor research consortium, has partnered with Mitsui Chemicals to commercialize carbon nanotube pellicles targeted for 600-watt-plus systems in the 2025 to 2026 timeframe. Whether they'll handle 1,000 watts remains to be seen.
Photoresists face similar challenges. Higher power enables faster exposures, but resist chemistry must balance sensitivity, resolution, and line-edge roughness—a tradeoff that becomes more acute at smaller feature sizes. Imec has developed yield models to address EUV stochastics (the randomness inherent in photon-limited exposures) and is co-optimizing resist formulations with process parameters. It's painstaking work.
Stage and reticle handling systems need upgrading too. High-NA tools use anamorphic optics that impose a 0.5× reduction in one dimension, requiring new mask formats, optical proximity correction strategies, and metrology. These are solvable engineering problems. But they take time and capital that not every chipmaker possesses.
Timing Matters
The 1,000-watt breakthrough arrives at a moment when semiconductor capacity constraints are acute. TSMC executives have indicated advanced-node capacity falls short of AI demand by a factor of three. CoWoS advanced packaging, essential for connecting AI chips to high-bandwidth memory, has doubled in capacity from roughly 35,000 to 40,000 wafers per month in 2024 to 70,000 to 80,000 in 2025, with plans to reach 100,000 to 150,000 by 2026. Yet supply remains tight.
Higher EUV throughput addresses one piece of the puzzle, perhaps the most critical piece. If ASML can deliver 330 wafers per hour by 2030, chipmakers gain the equivalent of adding more tools without the multi-year lead times or the cleanroom footprint. In an industry where a single advanced fab can cost $20 billion and take half a decade to bring online, that's no small thing.
Export controls complicate the landscape. The Netherlands has tightened restrictions on ASML's most advanced deep-ultraviolet systems to China, and U.S. controls have expanded to cover entities and technologies deemed strategic. China's reported progress on a crude EUV prototype—large, inefficient, and years from producing commercial chips—underscores the geopolitical stakes. ASML's lead in precision optics, source technology, and ecosystem integration remains insurmountable in the near term, though governments are clearly nervous.
Alternative lithography approaches are attracting capital, if not necessarily confidence. Canon's nanoimprint technology has shipped a system to the Texas Institute for Electronics, positioning itself as a lower-cost option for certain layers. U.S. startups like xLight, which received $150 million in federal incentives for a free-electron laser-based EUV source, and Substrate, pursuing X-ray lithography, represent long-shot challenges to ASML's dominance. Commercialization timelines for these technologies stretch into the 2030s, assuming they work at all.
The Path Runs Through Veldhoven
For now, and for the foreseeable future, the semiconductor industry's roadmap runs through a town in the Netherlands most people couldn't find on a map. ASML's 2030 revenue guidance of €44 billion to €60 billion, with gross margins between 56% and 60%, reflects confidence that EUV will remain the industry's unavoidable checkpoint.
The 1,000-watt source is a signpost, not a destination. It buys chipmakers time to scale production as demand accelerates, but only if pellicles, resists, and the rest of the ecosystem can keep pace. The semiconductor industry has a track record of solving impossibly hard problems when trillions of dollars hang in the balance.
This will be another test. Just perhaps not the final one.
