The pitch deck must have been something to see.
MatX, a chip startup barely two years old and led by a pair of former Google engineers, just convinced investors to hand over $500 million—for silicon that won't ship until 2027. The Series B, co-led by quantitative trading giant Jane Street and Leopold Aschenbrenner's Situational Awareness LP, values a company with no revenue, no customers, and crucially, no working chips at a level that would have seemed fantastical in the semiconductor world just five years ago.
What MatX does have: a promise. The kind that makes venture capitalists either reach for their checkbooks or run for the exits. They claim their chips will deliver ten times the performance of NVIDIA's GPUs for training and running large language models. Ten times. Not 10% better. Not twice as fast. A full order of magnitude improvement over the company that currently owns the AI chip market so thoroughly that competitors have largely stopped trying.
The question isn't whether that's ambitious. The question is whether it's achievable—or whether we're watching another generation of vaporware, this time wrapped in the technical credibility of two people who actually know how to build chips that work at scale.
When Pedigree Meets Promise
Reiner Pope and Mike Gunter aren't the typical Silicon Valley founders sketching chip architectures on cocktail napkins. Pope ran AI software for Google's Tensor Processing Units, the custom chips that power much of the company's machine learning infrastructure. Gunter designed TPU hardware. Between them, they've witnessed firsthand what separates elegant PowerPoint architectures from silicon that can survive a trillion-parameter training run without melting down or throwing errors every few hours.
That experience matters. It's one thing to claim revolutionary performance improvements from your garage. It's another to have actually shepherded chips through Google's production pipeline, where theoretical FLOPS meet the messy reality of power budgets, yield rates, and software stacks that need to work on day one.
Their design centers on the MatX One chip, purpose-built for the specific bottlenecks plaguing transformer models. The company's website talks about "highest FLOPS per square millimeter" and "most scale-up interconnect bandwidth" of any announced product. Weights stored in on-chip SRAM for ultra-low latency access. Key-value caches in high-bandwidth memory for the long context windows that make modern language models useful rather than merely impressive. Performance north of 2,000 output tokens per second on 100-layer mixture-of-experts models.
Those numbers would, indeed, reshape the economics of AI inference. If they're real. Right now, they're company claims on a website. No MLPerf benchmarks. No chips in customer data centers running actual workloads. Just architecture diagrams and the credibility that comes from having done this before—at Google, where the resource constraints looked very different than they do at a startup competing for TSMC's attention against customers with billion-dollar purchase orders.
The Bet Behind the Bet
Look at who's writing checks, and you start to understand the thesis MatX is selling.
Jane Street doesn't typically lead hardware rounds. The quantitative trading firm built its reputation on identifying market inefficiencies and exploiting them with mathematical precision. Their involvement signals they view AI compute scarcity not as a temporary squeeze but as a structural problem that will define the next decade of technology economics.
Aschenbrenner, who wrote an influential essay arguing that AI compute capacity would determine geopolitical power balances, is putting money where his manifesto is. The Collison brothers from Stripe are in. So is the investment partnership of Nat Friedman and Daniel Gross, who've become something like Silicon Valley's unofficial AI brain trust. Marvell Technology, the chip industry veteran, joined the round—perhaps seeing an opportunity, perhaps hedging against disruption.
What they're betting on isn't merely better silicon. It's a worldview that says NVIDIA's architectural choices, optimized over years for broad workload flexibility, necessarily leave performance on the table when you narrow the problem to transformer training and inference. MatX is designing from first principles around attention mechanisms, the mathematical core of how large language models work. No legacy. No obligation to run every workload reasonably well. Just one job: make transformers faster.
The timing gives the pitch urgency. Training runs now approach billion-dollar price tags, with research from 2024 pegging cost growth at 2.4 times annually since 2016. Meta disclosed plans to deploy 350,000 of NVIDIA's H100 GPUs by the end of last year just to remain competitive. When a 54-day training run for Llama 3 on 16,384 H100s suffered hundreds of interruptions from GPU and memory failures—a reality Mark Zuckerberg mentioned publicly—the case for purpose-built silicon starts sounding less like venture capital fantasy and more like operational necessity.
At some point, maybe, the economics force a reckoning.
The Green Giant Still in the Room
NVIDIA posted $130.5 billion in revenue for fiscal 2025. Data center sales alone hit $35.6 billion in the fourth quarter. Those aren't typos.
Their newest Blackwell platform claims four times the training performance and up to 30 times the inference speed of the previous Hopper generation—in specific large-scale configurations, naturally. MLPerf v5.0 results showed 2.2 to 2.6 times per-GPU speedups on select tasks, partial validation that NVIDIA's claims aren't purely marketing fiction. The GB200 NVL72 rack, with 72 GPUs and 130 terabytes per second of NVLink bandwidth, isn't just a product. It's an ecosystem: software libraries, networking knowledge, operational best practices refined across thousands of customer deployments over a decade.
AMD is mounting what looks like the first serious challenge to NVIDIA's dominance in years. The company's data center revenue reached $16.6 billion in 2025. Reports suggest AMD secured a multi-gigawatt chip deal with Meta that includes performance-based stock warrants potentially worth up to 10% of AMD's outstanding shares—the kind of creative deal structure that happens when customers desperately need alternatives to a monopoly supplier.
Google's Trillium TPUs claim over four times the training performance of the previous generation. They're now generally available on Google Cloud Platform, not just internal projects. AWS's Trainium3 UltraServers promise 4.4 times the compute performance over Trainium2. Microsoft's Maia 200 is ramping production in Azure data centers.
None of these players are sitting still. And all possess something MatX currently lacks: chips customers can order today, performance data from real deployments, and battle-tested software stacks that don't require rewriting your entire training pipeline.
The Manufacturing Reality
Even if MatX's architecture performs exactly as promised in simulation, the path from design validation to volume production remains treacherous. This is where well-funded hardware startups go to die.
TSMC's advanced packaging capacity—the CoWoS (Chip-on-Wafer-on-Substrate) process needed for integrating high-bandwidth memory with AI accelerators—remains scarce despite significant expansion. The foundry roughly doubled capacity from 35,000-40,000 wafers monthly in 2024 toward 80,000-120,000 monthly in 2026. Still insufficient to meet demand. NVIDIA holds substantial allocation, locked in through long-term contracts and volume commitments. So does AMD. The hyperscalers building custom chips have their own reserved slots.
MatX needs production capacity. They need HBM3E and HBM4 memory allocation, where SK hynix commands 62% market share and Samsung, Micron, and SK hynix are preparing for what industry watchers describe as a "battle year" in 2026. They need access to interconnect IP for building the hundred-thousand-chip clusters their website envisions. All while competing against customers representing billions in annual revenue to those suppliers.
The company's site mentions design targets for scale-out to "hundreds of thousands of chips." Getting the supply chain to actually manufacture that at volume? Different problem. Harder problem.
Then there's power, the constraint that might matter most. The International Energy Agency projects global data center electricity consumption will roughly double to 945 terawatt-hours by 2030, driven primarily by AI workloads. UK energy regulator Ofgem warned in February that proposed data center pipelines in Britain alone could match or exceed the country's peak electricity load. MatX's efficiency claims matter not just for performance bragging rights but for whether customers can physically plug the systems in without triggering utility grid concerns.
The Specialization Trap
By 2027, when MatX targets first shipments, the competitive landscape will look nothing like today's snapshot. NVIDIA will be shipping whatever architecture follows Blackwell Ultra. AMD's MI450 series will be in production. Google's TPU roadmap—already at v6e with rumors of v7 in development—marches forward. The hyperscalers iterate constantly on custom silicon.
MatX's advantage, if it materializes, stems from specialization. They're not building general-purpose accelerators that need to handle every possible workload. They're building chips designed for one narrow problem: transformer training and inference at frontier scale. The programming model described on their website promises direct developer control over memory hierarchies and dataflow—the kind of fine-grained optimization that could matter for research labs pushing the boundaries of what's trainable.
But specialization cuts both ways, and the history here isn't encouraging.
Groq demonstrated you can build SRAM-heavy inference chips hitting 240-276 tokens per second on Llama 70B with remarkably low latency. The tradeoff? Limited weight capacity per chip makes scale-out networking critical, and adoption remains modest. Cerebras built wafer-scale engines with 900,000 cores and 125 petaflops per chip—genuinely impressive engineering. Adoption: niche. SambaNova's DataScale platform claims five times GPU speed on 405-billion-parameter inference in vendor materials. Independent validation? Sparse.
The graveyard of specialized AI accelerators is crowded with architectures that worked beautifully in theory and foundered against the inertia of NVIDIA's CUDA ecosystem and the company's relentless execution in practice. Developers know CUDA. Universities teach CUDA. The tooling works. Switching costs are real.
The 2027 Reckoning
MatX has pedigree. They have capital—a staggering amount of it for a company with no shipping product. They have a technical thesis that's at least plausible enough to convince sophisticated investors including a quantitative trading firm that normally avoids hardware altogether.
Whether that's sufficient to deliver ten times NVIDIA's performance by 2027—at a price point, power envelope, and software maturity level that frontier AI labs will bet their billion-dollar training runs on—remains very much an open question. Perhaps more than one question, really.
Can they secure sufficient TSMC capacity without the purchasing power of incumbents? Will their specialized architecture translate theoretical advantages into real-world speedups on production workloads? Can they build a software ecosystem good enough that labs are willing to rewrite code optimized over years for NVIDIA's architecture? Will the claimed performance advantages survive contact with the messy reality of 24/7 data center operations?
And maybe the most uncomfortable question: What happens if NVIDIA's next two generations of chips close the gap before MatX ships their first one?
The company is betting half a billion dollars that they have answers. By 2027, we'll know if they were right.
