Bryce Neil and Jordon Kashanchi think the semiconductor industry is solving the wrong problem.
While giants like Cadence and Synopsys rush to bolt AI agents onto their decades-old design tools—each promising 10× productivity gains—the two founders of Visibl Semiconductors are betting on something else entirely. The real bottleneck in chip design, they argue, isn't a lack of clever algorithms or faster simulation engines. It's that nobody can talk to each other anymore.
Their solution, which emerged from stealth in late February as part of Y Combinator's Winter 2026 batch, is what they're calling "the coordination layer for chip design." An on-premises AI platform that ingests everything—code, specifications, scripts, cryptic tool outputs—and attempts to translate the chaos into something design teams can actually act on.
Whether a two-person startup can insert itself between the chip industry and the EDA oligopoly that's controlled it for three decades is, well, the question.
The Coordination Tax
Here's the problem Visibl is targeting: modern semiconductor design has become so complex that throwing more engineers at it doesn't work anymore. Or rather, it works less and less well.
Each additional engineer added to a chip project brings not just their productivity but also communication overhead. More meetings. More handoffs. More time spent figuring out what that error message from the timing analysis tool actually means, and whether fixing it will break something else three modules over.
"The bottleneck is no longer ideas, but execution throughput," reads the company's Y Combinator profile, a line that could double as either insight or jargon depending on who's reading it.
Visibl's platform is designed to absorb what Neil calls "the full design context"—the messy reality of code repositories, specification documents, build scripts, and the often maddeningly ambiguous feedback that EDA tools spit out. Then it decodes that feedback, validates potential changes, and packages everything for human review. Shorter iteration cycles, fewer late-stage disasters, and ideally a clearer path to tapeout, that critical moment when a chip design goes to manufacturing.
They've built something they call an "Orchestrator" application. Downloads and documentation exist on the company's website, though the real technical specifications—the details that would let you evaluate whether this thing actually works—remain behind the wall of client demos.
The Pedigree Problem (and Solution)
Kashanchi, who came on as CTO in late January or early February, brings exactly the kind of résumé that opens doors in semiconductor circles. He worked on Microsoft's custom AI silicon, the Azure Maia chips that power parts of the company's cloud infrastructure. Before that: stints at Arm and Intel, with deep experience in RTL (register-transfer level) design and chip architecture.
Neil's background is... different. Software and data systems work at Deloitte, focused on healthcare and public sector projects. It's not the typical semiconductor founder profile.
Perhaps that's the point. If the problem Visibl is solving lives at the intersection of chip design and data orchestration—and plenty of data engineering challenges disguise themselves as domain-specific problems—then maybe you need someone who's built coordination systems in other industries. Or maybe it's just an unusual pairing that happens to work.
The on-premises deployment model, which Neil emphasized when announcing Kashanchi's hire, matters more than it might seem. Semiconductor IP is guarded with the kind of paranoia usually reserved for nuclear launch codes. Design data represents billions in R&D investment and competitive advantage. The idea of sending it to anyone's cloud—even a trusted EDA vendor's—makes chip companies nervous in a way that's hard to overstate.
The Incumbents Move Fast
Visibl's timing, intentional or not, positions it right in the middle of an AI arms race.
Just two weeks before Visibl's emergence, Cadence Design Systems unveiled its ChipStack AI Super Agent, claiming productivity gains of up to 10× through what it calls "agentic workflows." The system orchestrates what Cadence describes as "multiple virtual engineers" across its suite of tools—Verisium for verification, Cerebrus for simulation, JedAI for design optimization.
Synopsys has been rolling out generative AI copilots throughout its EDA platform: automated assertion generation for formal verification, RTL code assistants, script optimization tools. By March 2025, the company was publicly discussing its "AgentEngineer" initiative, framing AI agents as the answer to an industry-wide talent shortage.
Siemens joined the party with its Questa One verification platform in May 2025, then expanded into broader agentic AI territory at the Design Automation Conference. The announcements included NVIDIA model integrations across its Solido and Calibre tools.
These aren't experimental features. They're production deployments, backed by companies with decades of customer relationships, massive installed bases, and the kind of market power that makes "industry standard" more than just marketing speak.
The Talent Crunch Is Real
The EDA vendors aren't making up the problem they claim to be solving.
McKinsey's analysis estimates the United States faces a shortfall of 59,000 to 146,000 semiconductor engineers and technicians by 2029, with demand accelerating sharply from 2025 forward. Chip designs are growing more complex—more transistors, more specialized IP blocks, more interactions to verify—while the pipeline of qualified engineers hasn't kept pace.
You can't just hire your way out anymore, which is partly why AI automation suddenly looks so appealing. Cadence, Synopsys, and Siemens all cite the same constraint: complexity increasing faster than talent supply.
Visibl is positioning itself not as a replacement for EDA tools but as something that sits above them. "Turn compute into capacity" is their framing—focus on coordination rather than trying to match feature sets with companies that have been building chip design software since the 1980s.
Whether that distinction is meaningful or just clever positioning remains to be seen.
Seeing Is Believing (Maybe)
The company is working the conference circuit, hunting for early customers. ISSCC in San Francisco from February 16-18 served as networking reconnaissance rather than a formal product launch. DVCon in Santa Clara (March 2-5) and NVIDIA's GTC conference in San Jose (March 16) are next on the calendar.
Y Combinator pushed out a LinkedIn post encouraging prospects to "book a demo at visiblsemi.com," adding the kind of confident claim that either ages brilliantly or becomes a cautionary tale: "Seeing Visibl in action will change how your team approaches chip design."
No customer names have surfaced publicly as of late February, which could mean early pilots under NDA or could mean the product is still in the "convince someone to try it" phase. Third-party funding databases show a $500,000 convertible note with Y Combinator listed as an investor, though the company hasn't confirmed details beyond its participation in the accelerator's Winter 2026 batch.
The Question That Matters
Can a two-person startup compete with Cadence, Synopsys, and Siemens?
The direct answer is probably no, not in any traditional sense of "compete." These companies have entrenched relationships with every major chip manufacturer, integration points throughout the design flow, and decades of accumulated domain knowledge baked into their tools.
But Visibl seems to be betting that the EDA giants' AI agents will remain siloed within their respective toolchains—Cadence agents optimizing Cadence workflows, Synopsys agents improving Synopsys tools. If that's true, maybe there's space for a coordination layer that orchestrates across all of them, handling the kind of cross-tool, cross-team judgment calls that currently require experienced human engineers.
The on-premises deployment model could provide an opening as well. Some semiconductor companies might prefer a startup's platform running entirely within their data centers over sending design data through an EDA vendor's cloud infrastructure, even if the vendor claims secure isolation. Trust matters in an industry where IP theft can kill a company.
Then again, the incumbents already offer on-premises deployment options. And they have far more integration points, far more data about how their tools actually get used, and far more resources to iterate quickly once they've identified a valuable feature.
Visibl will need to demonstrate clear, measurable value—genuine compression of iteration cycles, real reduction in those late-stage surprises that delay tapeout and cost millions. Saying you handle coordination is one thing. Proving you handle it better than the combination of existing tools plus experienced engineers is another.
The company is taking demos now. Chip design teams, famously skeptical and brutally pragmatic, will render their verdict soon enough. Either this particular bet on AI coordination has substance, or the race was already over before Visibl left the starting line.
In semiconductor startups, that's usually how it goes—fast answers, one way or the other.
